Various imager circuits have been proposed such as charge coupled device (CCD) arrays, complementary metal oxide semiconductor (CMOS) arrays, arrays combining both CCD and CMOS features, as well as hybrid infrared focal-plane arrays (IR-FPAs). Conventional arrays have light-sensing elements, typically referred to as “pixels” and readout circuitry that outputs signals indicative of the light sensed by the pixels.
A CMOS imager, for example, includes a focal plane array of pixel cells; each cell includes a photodetector (e.g., a photogate, photoconductor or a photodiode) overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a storage region, connected to the gate of the source follower transistor. Charge generated by the photodetector is sent to the storage region. The imager may also include a transistor for transferring charge from the photodetector to the storage region and another transistor for resetting the storage region to a predetermined charge level prior to charge transference.
FIG. 1 illustrates a block diagram of a CMOS imager device 908 having a pixel array 200 with each pixel cell being constructed as described above, or as other known pixel cell circuits. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 200. The row lines are selectively activated in sequence by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated in sequence for each row activation by a column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel.
The CMOS imager 908 is operated by a control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. Control circuit 250 also controls the row and column driver circuitry 210, 260 so that they apply driving voltages to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal Vrst taken off of the storage region when it is reset by the reset transistor and a pixel image signal Vsig, which is taken off the storage region after photo-generated charges are transferred to it. The Vrst and Vsig signals are read by a sample and hold circuit 265 and are subtracted by a differential amplifier 267, to produce a differential signal Vrst−Vsig for each pixel. Vrst−Vsig represents the amount of light impinging on the pixels. This difference signal is digitized by an analog-to-digital converter 275. The digitized pixel signals are fed to an image processor 280 to form a digital image output. The digitizing and image processing can be located on or off the imager chip. In some arrangements the differential signal Vrst−Vsig can be amplified as a differential signal and directly digitized by a differential analog to digital converter.
FIG. 2 illustrates a four transistor (4T) CMOS imager pixel cell 100. Pixel cell 100 includes a photodiode 102 connected to a transfer transistor 104. The transfer transistor 104 is also connected to storage region 108. A reset transistor 106, a capacitor 107 and a gate of a source follower transistor 110 are connected to storage region 108. A row select transistor 112 is connected to source follower transistor 110. The active elements of pixel cell 100 perform the functions of (1) photon to charge conversion by photodiode 102; (2) resetting the storage region to a known state before the transfer of charge to it by reset transistor 106; (3) transfer of charge to the storage region 108 by the transfer transistor 104; (4) selection of the cell 100 for readout by row select transistor 112; and (5) output and amplification of a signal representing a reset voltage (i.e., Vrst) and a pixel signal voltage (i.e., Vsig) based on the charges present on storage region 108 by source follower transistor 110. Capacitor 107 is utilized because charges produced during an integration period by photodiode 102 may be greater than the capacity of storage region 108. Accordingly, capacitor 107 provides additional charge storage capacity. The pixel cell 100 of FIG. 2 is formed on a semiconductor substrate as part of an imager device pixel array (e.g., array 200 of FIG. 1).
FIG. 3 illustrates a timing diagram for the FIG. 2 circuit 300 during pixel readout. Initially, the storage regions 108 of all pixels in an imager array 200 (FIG. 1) are set to a predetermined voltage to ensure that all source follower transistors 110 remain turned off. The ROW signal of the pixel intended to be read is pulsed high at time t1 providing an operating voltage across source follower transistor 110. The storage region 108 of the pixel intended to be sampled is then reset at time t2 by briefly turning on reset transistor 106, which is supplied with operating voltage VCC plus a Vt threshold voltage of the reset transistor 106 when signal RST goes high, thereby resetting storage region 108 to a predetermined voltage. The reset voltage level on the storage region 108 is then applied to the gate of source follower transistor 110, which converts it to a reset output voltage Vrst on a column output line. The output signal is subsequently sampled at time t3, for example by a sample and hold circuit 265 (FIG. 1), where a high pulse SHR is used to sample and hold the reset output voltage Vrst onto a first sample and hold capacitor.
Charge stored in photodiode 102 from an integration period is subsequently transferred to storage region 108 by signal TX going high at time t4 thereby, turning on transfer transistor 104. The transferred charge lowers the voltage on the storage region 108 to a pixel output signal level, which is applied to the gate of source follower transistor 110. Source follower transistor 110, which is supplied with operating voltage VCC, converts the signal voltage level to a signal output voltage Vsig on the column output line. Sample and hold circuit 265 (FIG. 1) in response to a sample/hold pulse SHS at time t5 causes the pixel's signal output voltage Vsig on the column line to be stored in a second sample and hold capacitor. After Vsig is sampled, the ROW signal is set to a low voltage and the pixel circuit is ready for a next image capture.
Since transfer transistor 104 is positioned between photodiode 102 and storage region 108, the storage region 108 can be reset prior to transferring electrons. This permits a correlated double sampling operation resulting in reduced kTC noise and image noise.
With the pixel circuit configuration of FIG. 2 during reset, in order to obtain a maximum voltage swing at storage region 108, the reset transistor gate voltage is boosted to VCC+Vt (a threshold voltage of reset transistor 106). By adding voltage Vt to the reset voltage, the storage region 108 can be reset to VCC allowing a greater output signal swing from the source follower transistor 110 in response to charges transferred to the storage region 108 from photodiode 102. This technique requires additional supply voltage boost circuits to boost the reset voltage which increases the size, power consumption, design complexity and costs of the pixel and associated circuit.